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The
simulation of logic
designs is a very
important part of
the VLSI design
process. Determining
the behavior of the
final product ahead
of time is essential
in speeding up
design cycles,
improving yields,
and reducing
development costs.
Unfortunately, as
designers push
toward ever smaller
design rules,
simulation times
have been becoming
very challenging.
Logic
Pixels Inc. has been
developing a fast,
flexible, and
affordable
functional
verification
software tool for
VLSI chip design.
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